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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Requirements
Table 13:
Burst READ Cycle Timing Requirements
104 MHz
80 MHz
Parameter 1
Symbol
Min
Max
Min
Max
Units
Notes
ABA
Burst to READ access time
t
35
46.5
ns
CLK to output delay
t
ACLK
7
9
ns
BOE
Burst OE# LOW to output delay
t
20
20
ns
CE# HIGH between subsequent burst and
t
CBPH
5
5
ns
2
mixed-mode operations
Maximum CE# pulse width
t CEM
8
8
μs
CE# LOW to WAIT valid
t
CEW
1
7.5
1
7.5
ns
CSP
CLK period
CE# setup time to active CLK edge
Hold time from active CLK edge
Chip disable to DQ and WAIT High-Z output
t CLK
t
t HD
t HZ
9.62
3
2
20
20
8
12.5
4.5
2
20
20
8
ns
ns
ns
ns
3
CLK rise or fall time
CLK to WAIT valid
Output HOLD from CLK
CLK HIGH or LOW time
t KHKL
t KHTL
t KOH
t KP
2
3
1.6
7
2
4
1.8
9
ns
ns
ns
ns
Output disable to DQ High-Z output
Output enable to Low-Z output
Setup time to active CLK edge
t OHZ
t OLZ
t SP
3
3
8
3
3
8
ns
ns
ns
3
4
Notes:
1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0b).
2. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be pro-
vided every t CEM. A refresh opportunity is satisfied by either of the following two condi-
tions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns.
3. Low-Z to High-Z timings are tested with the circuit shown in Figure 25 on page 32. The
High-Z timings measure a 100mV transition from either V OH or V OL toward V CC Q/2.
4. High-Z to Low-Z timings are tested with the circuit shown in Figure 25 on page 32. The Low-
Z timings measure a 100mV transition away from the High-Z (V CC Q/2) level toward either
V OH or V OL .
PDF: 09005aef81cb58ed/Source: 09005aef81c7a667
16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN
34
Micron Technology, Inc., reserves the right to change products or specifications without notice.
?2005 Micron Technology, Inc. All rights reserved.
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